1. Field of the Invention
The present invention relates to a multi-processor system apparatus using two or more processors and particularly to a multi-processor system apparatus which has groups of processor and memory modules interconnected with multiple stages of switching (i.e. a multi-stage interconnection network).
2. Description of the Prior Art
A multi-processor system apparatus having groups of processor and memory modules interconnected by switching elements may take a more duration of time for data processing when two or more data packets are received by a single switching element causing collision of data, thus declining the efficiency of the data processing. For compensation, some schemes including non-blocking network, re-arrangeable network, and blocking network have been suggested for minimizing the event of packet data collision in a switch.
The non-blocking network such as crossbar network or Clos network may avoid any collision of data in a switch when the concentration of call lines is inhibited by scheduling. Also, the re-arrangeable network may allow no collision when the setting of switching elements is controlled by scheduling. Whereas, the blocking network may generally eliminate any collision with not simply scheduling but scheduling of a pattern of access demands.
However, the non-blocking network becomes large in the hardware arrangement to meet the number of processor and memory modules and will be increased in the cost of large-scale system production. Although its hardware cost is smaller than the non-blocking network, the re-arrangeable network requires more time for the scheduling and will hardly be compatible with a multi-processor system. Additionally, as the scheduling process of the blocking network generally allow no collision through re-arranging patterns of access demands, its practical action on the multi-processor system is limited to only a particular case where demanding factors are aligned in a given order.